Cyclotron is a Rust-based functional simulator for the Radiance GPU architecture at UC Berkeley. This project extends it with a timing layer to be a cycle-accurate performance model. We wrap around the existing core simulator using chained, parametrized timing queues to model shared resources like global and shared memory. This allows us to capture realistic latency, bandwidth, and backpressure without changing the underlying functional execution.

The project aims to help create a closed-loop neuromodulation system that epidurally stimulates the brain. By analyzing cognitive/behavioral changes and identifying which forms of stimulation are effective we could improve therapeutic outcomes. However when stimulation is applied, significant artifacts occur which corrupt the neural data. This research aims to investigate the removal of these artifacts from recorded signals along with any other noise contaminating the data.

To be written.

I taped out two 16nm CMOS multi-processor RISC-V SoCs (one ML and one DSP focused) as part of UC Berkeley’s Spring 25 EE 194 Tapeout class. I was part of the Integration team and my work centered on top-level IP integration, physical design, and the Network-on-Chip (NoC). I built and benchmarked custom NoC topologies for the two chips, by extending the open-source Constellation framework, which was later also pushed upstream.

I built a digital blind clock and data recovery (CDR) block for a USB 2.0 Hi-Speed (480 Mb/s) receiver, in Chisel which was targeted for the SKY130 process. The design uses 5x oversampling and a center-picking phase selection strategy to recover bits quickly without a PLL/DLL, and corrects for jitter using an Add-Drop FIFO.

This project builds a priority-aware DVFS controller for a Network-on-Chip (NoC) to keep latency critical (control) traffic responsive while enforcing hard power caps in the context of Warehouse-Scale-Computers. I extend Sniper and Booksim 2.0 for trace-driven simulation and compare class-aware DVFS controllers to a baseline uniform throttling strategy. I show that class class-aware DVFS lowers control P99 tail latency under the same power budget.

This project is a 3-stage, in-order RISC-V CPU in Verilog (IF → Decode/Execute → Mem/Writeback) targeting the Sky130flow. It includes a direct-mapped instruction cache + data cache and a stall/flush scheme for hazards and cache misses. It also implements forwarding paths to eliminate common data hazards and added system features like CSR writes. The design was taken through synthesis and place-and-route, reporting post-PAR timing and PPA.

This was a cleanroom micofabrication lab project, where I fabricated a MOS test-chip on a 3-inch <100> p-type silicon wafer using a multi-mask process (ACTV, POLY, CONT, METL). I went through the steps of photolithography, wet etching, thermal oxidation, dopant diffusion, and aluminum metallization/patterning. Afterwards I electrically characterized the resulting resistors, MOS capacitors, diodes, MOSFETs, and an inverter using probe-station measurements.

Built a controller that balances an inverted pendulum upright on a moving cart. I modeled the system, tuned the controller, ran it on real hardware, and tested stability and tracking by pushing the pendulum and commanding the cart to follow position references.

Modeled an unstable hovering plant by experimentally identifying a linearized transfer function around an equilibrium height, then designed an analog compensator to stabilize it. Using a photoresistor position sensor, an op-amp controller chain, and a current amplifier driving an electromagnet, I tuned offsets and loop dynamics to successfully levitate a steel ball.

Built a pipelined RISC-V CPU in Logisim which implemented core datapath blocks: ALU, 32-register regfile, and an immediate generator. It extended the CPU to support RISC-V instructions (ALU ops, branches, loads/stores, and jumps). Added basic pipeline hazard handling by flushing wrong-path instructions on taken branches/jumps using a no-op.

Extended the PintOS educational OS by implementing core kernel features spanning user program support, system calls, file I/O, floating-point context switching, and thread scheduling. Some highlights include user-memory validation for syscalls, process creation/exec/wait semantics, a full file-descriptor interface, saving/restoring FPU state across context switches, and kernel-level scheduling improvements (efficient sleeping, strict priority scheduling, and priority donation).

I built and evaluated multiple compression algorithms to transmit animated PNG (APNG) videos over a very-low bandwidth radio link (APRS/AX.25 via Direwolf on a Raspberry Pi), then reconstruct and decompress it server-side. I explored both lossless and lossy methods (LZW, DEFLATE/LZ77 + Huffman, JPEG2000-style wavelets, and SPIHT), and primarly focused on implementing SPIHT-based wavelet compression for color video frames.

To be written.

A mathematical library for scientific computing in Java, with a focus on Linear Algebra and Abstract Algebra. Comprehensive support for numerical algorithms over abstract algebraic sturctues (Groups, Rings, Fields).

A full-fledged web browser that supports several URI schemes, Search, Hyperlinks, Cookies, Multithreading, and a graphical interface.

To be written

Implement a version-control system mimicing Git from scratch. Users can save the contents of entire directories in commits, restore different versions, view history, branch, and merge.

Construct a robot car that listens to voice commands and then drives on the command’s pre-defined path.

An interpreter for a subset of the scheme language. Able to evaluate various expressions and call built-in procedures. Support logical special forms and tail call optimization.